1. Field of the invention
The present invention relates to a thin-film-transistor (abbreviated hereafter to TFT)-array substrate and a liquid-crystal display device. More particularly, the present invention relates to the structure of a TFT-array substrate capable of solving a problem that arises when a contact hole of a TFT is formed by boring a film using a dry-etching technology.
2. Description of the Related Art
FIG. 7 is a diagram showing one of a pair of substrates sandwiching a liquid crystal in a conventional ordinary TFT liquid-crystal display device. To be more specific, FIG. 7 shows a typical structure of a TFT-array substrate including inverted-stagger TFTs, gate wires and source wires. As shown in the figure, in the TFT-array substrate 60, the gate wires 50 and the source wires 51 are provided to form a matrix on a transparent substrate. A square area enclosed by two parallel adjacent gate wires 50 and two parallel adjacent source wires 51 serves as a pixel 52 on which a TFT 53 is provided.
As shown in the figure, on the TFT 53, there is provided a gate electrode 54 protruding out off a gate wire 50. A gate insulation film covers the entire surface of the gate electrode 54. A semiconductor active film 55 is provided on the gate insulation film above the gate electrode 54. A drain electrode 57 and a source electrode 56 are provided over a space spread over the top surface of the gate insulation film to the top surface of the semiconductor active film 55. The source electrode 56 protrudes out off the source wire 51. A passivation film is provided to cover the TFT 53 comprising the source electrode 56, the drain electrode 57 and the gate electrode 54. A contact hole 58 is formed by boring the passivation film on the drain electrode 57. There is also provided a pixel electrode 59 made of a transparent conductive film. The pixel electrode 59 is electrically connected to the drain electrode 57 trough the contact hole 58.
FIG. 7 shows a top view of the leftmost top pixel of the TFT matrix unit on the TFT-array substrate 60. The end of each gate wire 50 is extended to the outside of the TFT matrix unit or to the left side on the figure. At the end of the extension, a gate terminal pad 61 is provided for connecting the gate wire 50 to a gate driver for driving the gate wire 50. It should be noted that the gate driver itself is not shown in the figure. Each source wire 51 is configured in the same way as the gate wire 50 except that the end of the source wire 51 is extended to the outside of the TFT matrix unit or in the upward direction on the figure. At the end of the extension, a source terminal pad 62 is provided for connecting the source wire 51 to a source driver (not shown) for supplying a signal to the source wire 51. At the locations of the gate terminal pad 61 and the source terminal pad 62, lower pad layers are provided. The lower pad layers are each a wiring layer created to form a single body with the gate wire 50 or the source wire 51. A contact hole is formed by boring the passivation film covering the each of the lower pad layer so that the lower pad layer is exposed to any upper layer created thereon. An upper pad layer electrically connected to the lower pad layer through the contact hole is normally provided.
As described above, on the TFT-array substrate, there are provided a contact hole for electrically connecting the drain electrode of the TFT to the pixel electrode, and a contact hole for electrically connecting each lower pad layer and an upper pad layer at the locations of the gate terminal pad and the source terminal pad. Normally, these contact holes are formed by boring the passivation films by using the dry-etching technique during a process to fabricate the TFT-array gate. Specifically, the contact hole at the location of the gate terminal pad is formed by boring both the gate insulation film and the passivation film by applying the dry-etching technique.
In general, when the dry-etching technique is applied using an etching apparatus, however, there is observed a phenomenon wherein a substrate being processed is electrically charged because the substrate is exposed to a plasma generated in a chamber of the etching apparatus. In addition, the electric charge is not spread uniformly over the whole surface of the substrate being processed for a variety of reasons, resulting in a distribution of electrical charge on the surface.
Thus, also in a dry-etching process to form the contact holes described above, the drain electrode exposed during the formation of the contact holes or the lower pad layers beneath the gate and source terminal pads are electrically charged. As a result, the gate and source wires are electrically charged. In the case of the contact hole on the drain electrode, the contact hole on the gate terminal pad and the contact hole on the source terminal pad, the locations of the holes are separated from each other. Thus, there are differences in electric-charge amount between the drain electrode and the gate and source wires due to an effect of the electric-charge distribution on the surface created by the plasma, generating differences in electric potential between them. Even though FIG. 7 shows only one pixel, in actuality, there are a number of pixels on the TFT-array substrate, and the drain electrodes of TFTs on the pixels have different amounts of electric charge due to the distribution of electric charge on the surface.
In such a state, in spite of the fact that no voltage is applied during an operation to drive the TFT-array substrate, a difference in electric potential has already been generated between the drain electrode and the source electrode of each TFT at a stage the TFT-array substrate is completed. In addition, the difference in electric potential generated between the drain electrode and the source electrode varies from TFT to TFT on the TFT-array substrate, raising a problem that surface variations in characteristics among the TFTs on the TFT-array substrate increase in magnitude and number.
Moreover, the difference in electric-charge amount between the gate terminal pad and the source terminal pad results in a difference in electric potential between the gate wire and the source wire at locations sandwiching the gate insulation film. In the case of a large difference in electric potential between the gate wire and the source wire, it is feared that the insulation of the gate insulation film at a location of an intersection of the gate and source wires is broken.
Normally, in order to eliminate adverse effects of electric charge generated by a plasma during a dry-etching process on characteristics of a TFT, an anneal treatment is introduced in any process following the dry-etching process as a countermeasure. It is desirable, however, to provide a TFT-array substrate which can be produced by eliminating adverse effects caused inherently electric charge generated by a plasma without carrying out an anneal treatment as an additional process. In addition, there is also raised a problem caused by the fact. that, the larger the size of the substrate, the greater the variations of electric charge generated by the plasma on the surface. It is thus desirable to provide a proper solution to this problem.